^A^D^OTECHNICAL INFO ON MODULE #3 CON'T^P
The following is technical informaton from the Coleco Vision Technical
Manual.^E  NOTE ! While this is NOT for the standalone unit but for the
coleco vision unit only, there are obvious similarities between the two
systems.   CON'T. FROM LAST ISSUE.
The Z-80A uses two busses, address and data. The Address Bus (A0-Al5)
provides addresses for the memory (upto 64K bytres unidirectional ) data
exchanges and for I/O device data exchanges.  The Data Bus (D0-D7)
consists of an 8 bit tri-state bidirectional data bus. It is used for
data exchanges with emmroy and I/O devices.
 
In Addition to the two busses the Z-80A has several control signals.

MACHINE CYCLE ONE (Ml) indicates the current machine cycle is the OP code
fetch cycle of an instruction execution. Ouput, active low.

MEMORY REQUESST (MREQ) signal indicates the address bus holds a valid
address for a memory read or memory write operation. Tri-state output,
active low.

INPUT/OUTPUT REQUEST(IORQ) signal indicates the lower half of the address
bus holds a valid I/O address for an I/O read or write operations. An
IORQ signal is also generated when an interrupt is being acknowledged to
indicate that an interrupt response vector can be placed on the data bus.
Tri-state output, active low.

MEMORY READ(RD) indicates the CPU wants to read data from memory or an
I/O device.  The addressed I/O device or memory should use this signal to
gate data onto the CPU data bus. Tri-state output, active low.
 
MEMORY WRITE (WR) indicates the CPU data bus holds valid data to be
stored in the addressed memory or I/O device.  Tri-state output, active
low.
REFRESH (RFSH) indictes the lower seven bits of the address bus contain a
refresh address for dynamic memories and the current MREQ signal should
be used to do a refresh read to all dynamic memories. Output active low.

HALT STATE (HALT) indicates the CPU has executed a HALT software
instruciton and is awaiting either a non-maskable or a maskable interrupt
(with the mask enabled) before operation can resume.  While halted, the
CPU executes NOP's to maintain memory refresh activity. Output, active
low.

WAIT (WAIT) indicates to the Z-80A CPU that the addressed memory or I/O
devices are not ready for data transfer. The CPU continues to enter wait
states for as long as this signal is active. Input active low.

INTERRUPT REQUEST (INT) signal is generated by I/O devices. A request
will be honored at the end of the current instruction if the internal
software controlled interrupt enaable flip-flop (FF) is enabled. Input,
active l0w.

^DTHERE IS MUCH MORE OF THIS TYPE INFORMATION IN THE TECH MANUAL.
HOWEVER, UNLESS SOME FEEDBACK IS RECEIVED INDICATING THAT YOU WISH MORE
OF THIS &/OR CAN MAKE ANY SENSE OF IT, THIS WILL BE THE LAST OF THIS
SERIES.  NOT TO BE CONTINUED UNLESS REQUESTED.
 
^B

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